1. Field
Exemplary embodiments of the present invention relate to a bank selection circuit that increases the operation speed of a memory device, and the memory device having the same.
2. Description of the Related Art
In a system including a plurality of semiconductor devices, a memory device is used for data storage. If a memory controller such as a central processing unit (CPU) or a graphics processing unit (GPU) applies a command and an address for data input/output to the memory device, the memory device performs an operation for storing data input from the controller in a memory cell area corresponding to the input address, or the memory device performs an operation for outputting data stored in the memory cell area corresponding to the address.
FIG. 1 is a configuration diagram of a memory device including a bank selection circuit according to the conventional art, and FIG. 2 is a timing diagram illustrating the active operation of the memory device of FIG. 1. With reference to FIG. 1 and FIG. 2, an operation for activating a specific word line in the memory device and the features of the conventional art will be described.
Referring to FIG. 1, the conventional memory device includes a command latch unit 101, a command decoder 103, a delay unit 105, an address latch unit 107, a bank address decoder 109, a bank selection unit 111, and a core area 113. The core area 113 may include 8 banks (not illustrated in FIG. 1).
The command latch unit 101 is formed of a through-type latch, latches an input command CMD, and transfers a latched command CMD_LA to the command decoder 103.
The configuration of the through-type latch is illustrated in FIG. 3A. As illustrated in FIG. 3A, a pass gate 301 is turned on when a clock CLK is ‘low’, and the input signal CMD is directly latched and is stored until a next signal is input.
The command decoder 103 receives and decodes a latched command CMD_LA to generate an active operation signal ACT.
The delay unit 105 delays the active operation signal ACT for a designated time and transfers a delayed active operation signal ACTD to the bank selection unit 111.
The address latch unit 107 is formed of an edge trigger-type latch, and latches an address ADD, which is input together with the command CMD, at the rising edge of the clock CLK. The address ADD is divided into a bank address BA and a row address RA, and the address latch unit 107 latches the bank address BA and the row address RA. A latched bank address BA_LA is transferred to the bank address decoder 109 and a latched row address RA_LA is transferred to the core area 113.
The edge trigger-type latch is illustrated in FIG. 3B. As illustrated in FIG. 3B, a first pass gate 303 is turned on when a clock CLK is ‘low’, and an input signal ADD is stored in a first latch 305. Subsequently, a second pass gate 307 is turned on at the rising edge of the clock CLK, and the signal ADD is transferred to a second latch 309. Finally, a latch signal ADD_LA is stored from the rising edge of the clock CLK.
The bank address decoder 109 decodes the bank address BA to generate bank selection signals BAI<0:7>. The 8 bank selection signals BAI<0:7> correspond to the 8 banks in the core area 113, respectively.
The bank selection unit 111 receives the delayed active operation signal ACTD from the delay unit 105 and transfers the delayed active operation signal ACTD to a bank selected by the bank selection signals BAI<0:7>. 8 bank active operation signals ACT_B<0:7> output from the bank selection unit 111 correspond to the 8 banks in the core area 113, respectively.
As described above, the command latch unit 101 and the address latch unit 107 latch input signals at different timings, respectively. In detail, as illustrated in FIG. 2, the through-type command latch unit 101 latches the input command CMD at a time earlier than the rising edge of a clock CLK by a setup time tIS. Meanwhile, the edge trigger-type address latch unit 107 latches the address ADD at the rising edge of the clock CLK.
Thus, in the through-type latch, the latch timing is earlier than the edge trigger-type latch. However, since a signal synchronized with the clock CLK is not used in the through-type latch, a variation of the latch timing is large. Meanwhile, in the edge trigger-type latch, the latch time is delayed as compared with the through-type latch. However, since the edge trigger-type latch may operate in synchronization with the clock CLK, a setup/hold time is easy to adjust. In this regard, when the address is input through a plurality of pins, the edge trigger-type latch has been used because adjusting the setup/hold time is easy in consideration of a large pin variation. In addition, the delay unit 105 is further provided to delay the active operation signal ACT for a designated time in order to allow the active operation signal ACT and the bank selection signals BAI<0:7> to coincide with each other when applied to the bank selection unit 111 in consideration of the fact that the address ADD is delayed and latched as compared with the command CDM.
Due to the delay unit 105, the conventional memory device is significantly affected by PVT (process, voltage, and temperature). More specifically, when power noise occurs and a power supply voltage level is reduced, the delay amount of the delay unit 105 is significantly increased and the timings of the delayed active operation signal ACID and the bank selection signals BAI<0:7> may not coincide with each other.
To increase the operation speed of a memory device, a method for improving an AC parameter such as tRCD (RAS to CAS Delay) may be provided.